As an experienced Design & Verification Engineer Engineer, you will be part of the hardware platform team that builds development platforms for leading CPU and System IP products that target both silicon and FPGA implementations for this six month contract.

Key to success in this role is the ability to apply your RTL design skills using SystemVerilog for FPGA and/or ASIC, together with an understanding of FPGA device architecture. For verification you will be using System-Verilog and possibly UVM. This will include coding System Verilog Assertions (SVA) checks, cover-properties, SV coverage groups etc.

You will be part of a large team working within a complex development environment. UNIX/Linux skills alongside scripting languages like Python, Tcl, Make, bash etc will also be required.

Required skills and experience

• Proven experience of delivering RTL designs in an SoC or FPGA
• RTL Verification at both unit and system level, using SV including SVA
• Experience of ASIC or FPGA synthesis tools
• Unix / Linux skills including shell programming/scripting in e.g. Make, Python, Tcl, sh, bash.

“Nice to have” skills and experience:

• C programming skills is a plus, ideally, some grounding in assembly language and object-orientated coding (e.g. C++)
• Experience with the implementation of ASIC/SoC RTL in FPGA
• SV UVM test benches, using UVM Verification IPs
• Xilinx FPGA technology
• Synopsys tool flows

If you have the required experience and want to be part of a team that helps build innovative products that impact millions of people, then we would love to hear from you.

Please note, hybrid working places are in place for this role, with 2 days onsite (Cambridge) required each week.