If you enjoy pushing the boundaries within the fast-moving world of IP Verification then this could be a great contract opportunity for you..  Working as a Formal Verification Engineer within an industry leading System Memory Management Product team you will be responsible for developing new hardware verification testbenches for future generation hardware IP, with a focus on improving performance, quality and efficiency.

What you’ll be doing 

• Review proposed design changes from a verification complexity perspective.
• Support the verification environment from investigation through to verification closure
• Develop, maintain, and improve the SVA Formal testbenches
• Develop, maintain and improve the suite of SVA Protocol Checkers for Formal and Simulation use

Required Skills and Experience

• Proven experience of delivering formal verification environments for complex IP/module level designs.
• Property-based model-checking or Formal Property verification
• Experience of writing assertions using SystemVerilog Assertions (SVA) using formal tools (e.g. Cadence, Mentor, Synopsys tools).

 ‘Nice To Have’ Skills and Experience

• Multiprocessing microarchitecture experience with knowledge of cache coherence and bus protocols (e.g. AMBA5 CHI, AMBA4 ACE or AXI

Please note, hybrid working places are in place for this role, with 2 days onsite (Manchester) required each week.  The role will also be Inside IR35, working via an umbrella company.

If you have the required experience and want to be part of a team that helps build innovative products that impact millions of people, then please get in touch with us today.